Chipset designs such as some Intel Input/Output Controller Hub (ICH) designs include an implementation of PCI-Express (PCIe) ports that is not modular, and thus not scalable. As an example, the shared buffer in some Intel ICH designs is only shared with four PCIe ports, and there is not any flexibility to expand the number of PCIe ports beyond four. This makes it extremely difficult to design, for example, a new System On Chip (SOC) with a different number of PCIe ports. For example, if a new SOC design requires five PCIe ports, a major effort is necessary in order to convert the four ICH PCIe ports to five ICH PCIe ports for the new SOC design. Additionally, it is not convenient to reduce the number of PCIe ports to less than four. If a new SOC requires only three PCIe ports and it has to adopt an ICH design that includes four PCIe ports, an additional cost of integrating the fourth port is necessary.